RTL Academy

What Happens Between RTL and Bitstream

A vendor-neutral tour of the FPGA toolchain (elaboration, synthesis, placement, routing, timing analysis, and bitstream generation) for people who've always treated the build as a black box.

Clock Domain Crossing: When the RTL Is Right and the Build Is Wrong

The synchronizer you wrote is a request; the netlist is what ships. ASYNC_REG, clock-group and max-delay exceptions, Gray-bus skew constraints, CDC reports, and reset sequencing after PLL lock: the half of CDC that lives in the tools rather than the RTL.

Clock Domain Crossing: Every Way to Get It Wrong

A tour of the single most common source of silent, intermittent, impossible-to-reproduce bugs in digital design, and the handful of techniques that actually fix them.

A Nanosecond Is a Distance: Latency Budgets from First Principles

Every nanosecond in a low-latency system is a real thing you can point to: a stretch of fiber, a gate delay, a queue. This article builds a physical mental model of where time goes.