<?xml version="1.0" encoding="UTF-8"?>
<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
<url>
<loc>https://rtl.academy/</loc>
<changefreq>weekly</changefreq>
<priority>1</priority>
</url>
<url>
<loc>https://rtl.academy/privacy</loc>
<changefreq>yearly</changefreq>
<priority>0.2</priority>
</url>
<url>
<loc>https://rtl.academy/career</loc>
<lastmod>2026-10-05T02:29:19.068Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-design-pipeline</loc>
<lastmod>2026-10-05T02:29:18.600Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/glossary</loc>
<lastmod>2026-10-05T02:29:04.091Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/tool-setup</loc>
<lastmod>2026-10-05T02:29:04.067Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sdc-reference</loc>
<lastmod>2026-10-05T02:29:04.043Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog-reference</loc>
<lastmod>2026-10-05T02:29:04.020Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl-reference</loc>
<lastmod>2026-10-05T02:29:03.994Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/motor-control</loc>
<lastmod>2026-10-05T02:29:03.952Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cryptography</loc>
<lastmod>2026-10-05T02:29:03.925Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ml-acceleration</loc>
<lastmod>2026-10-05T02:29:03.900Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/communications</loc>
<lastmod>2026-10-05T02:29:03.875Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/image-processing</loc>
<lastmod>2026-10-05T02:29:03.851Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/advanced-architecture</loc>
<lastmod>2026-10-05T02:29:03.807Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verification</loc>
<lastmod>2026-10-05T02:29:03.781Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hls</loc>
<lastmod>2026-10-05T02:29:03.754Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/embedded-processors</loc>
<lastmod>2026-10-05T02:29:03.729Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-interfaces</loc>
<lastmod>2026-10-05T02:29:03.702Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/high-speed-serial</loc>
<lastmod>2026-10-05T02:29:03.678Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dsp</loc>
<lastmod>2026-10-05T02:29:03.650Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/optimization</loc>
<lastmod>2026-10-05T02:29:03.604Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ip-cores</loc>
<lastmod>2026-10-05T02:29:03.577Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/bus-architectures</loc>
<lastmod>2026-10-05T02:29:03.551Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/pipelining</loc>
<lastmod>2026-10-05T02:29:03.525Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cdc</loc>
<lastmod>2026-10-05T02:29:18.996Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-closure</loc>
<lastmod>2026-10-05T02:29:03.452Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/projects</loc>
<lastmod>2026-10-05T02:29:03.300Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/debugging</loc>
<lastmod>2026-10-05T02:29:03.274Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/io-interfaces</loc>
<lastmod>2026-10-05T02:29:03.235Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/clocking</loc>
<lastmod>2026-10-05T02:29:03.210Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-design</loc>
<lastmod>2026-10-05T02:29:03.186Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sync-design</loc>
<lastmod>2026-10-05T02:29:03.161Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-boards</loc>
<lastmod>2026-10-05T02:29:03.116Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/open-source-tools</loc>
<lastmod>2026-10-05T02:29:03.090Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-flow</loc>
<lastmod>2026-10-05T02:29:03.065Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-families</loc>
<lastmod>2026-10-05T02:29:03.040Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-architecture</loc>
<lastmod>2026-10-05T02:29:03.015Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-patterns</loc>
<lastmod>2026-10-05T02:29:02.970Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/simulation</loc>
<lastmod>2026-10-05T02:29:02.942Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/systemverilog</loc>
<lastmod>2026-10-05T02:29:02.916Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog</loc>
<lastmod>2026-10-05T02:29:02.890Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl</loc>
<lastmod>2026-10-05T02:29:02.861Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-intro</loc>
<lastmod>2026-10-05T02:29:02.833Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-basics</loc>
<lastmod>2026-10-05T02:29:18.922Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/state-machines</loc>
<lastmod>2026-10-05T02:29:18.846Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sequential-logic</loc>
<lastmod>2026-10-05T02:29:18.765Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/combinational-logic</loc>
<lastmod>2026-10-05T02:29:18.511Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/boolean-algebra</loc>
<lastmod>2026-10-05T02:29:18.429Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/number-systems</loc>
<lastmod>2026-10-05T02:29:18.665Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cdc/when-the-rtl-is-right-and-the-build-is-wrong</loc>
<lastmod>2026-10-05T02:29:18.136Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/timing-basics/a-nanosecond-is-a-distance</loc>
<lastmod>2026-10-05T02:29:16.680Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/cdc/clock-domain-crossing-every-way-to-get-it-wrong</loc>
<lastmod>2026-10-05T02:29:17.912Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/fpga-design-pipeline/what-happens-between-rtl-and-bitstream</loc>
<lastmod>2026-10-05T02:29:12.106Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
</urlset>
