<?xml version="1.0" encoding="UTF-8"?>
<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
<url>
<loc>https://rtl.academy/</loc>
<changefreq>weekly</changefreq>
<priority>1</priority>
</url>
<url>
<loc>https://rtl.academy/privacy</loc>
<changefreq>yearly</changefreq>
<priority>0.2</priority>
</url>
<url>
<loc>https://rtl.academy/career</loc>
<lastmod>2026-07-28T14:48:58.629Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-design-pipeline</loc>
<lastmod>2026-07-28T14:48:58.293Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/glossary</loc>
<lastmod>2026-07-28T14:48:44.223Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/tool-setup</loc>
<lastmod>2026-07-28T14:48:44.189Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sdc-reference</loc>
<lastmod>2026-07-28T14:48:44.155Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog-reference</loc>
<lastmod>2026-07-28T14:48:44.125Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl-reference</loc>
<lastmod>2026-07-28T14:48:44.098Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/motor-control</loc>
<lastmod>2026-07-28T14:48:44.049Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cryptography</loc>
<lastmod>2026-07-28T14:48:44.021Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ml-acceleration</loc>
<lastmod>2026-07-28T14:48:43.990Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/communications</loc>
<lastmod>2026-07-28T14:48:43.962Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/image-processing</loc>
<lastmod>2026-07-28T14:48:43.933Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/advanced-architecture</loc>
<lastmod>2026-07-28T14:48:43.885Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verification</loc>
<lastmod>2026-07-28T14:48:43.856Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hls</loc>
<lastmod>2026-07-28T14:48:43.826Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/embedded-processors</loc>
<lastmod>2026-07-28T14:48:43.796Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-interfaces</loc>
<lastmod>2026-07-28T14:48:43.765Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/high-speed-serial</loc>
<lastmod>2026-07-28T14:48:43.738Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dsp</loc>
<lastmod>2026-07-28T14:48:43.711Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/optimization</loc>
<lastmod>2026-07-28T14:48:43.664Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ip-cores</loc>
<lastmod>2026-07-28T14:48:43.637Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/bus-architectures</loc>
<lastmod>2026-07-28T14:48:43.609Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/pipelining</loc>
<lastmod>2026-07-28T14:48:43.581Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cdc</loc>
<lastmod>2026-07-28T14:48:58.582Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-closure</loc>
<lastmod>2026-07-28T14:48:43.494Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/projects</loc>
<lastmod>2026-07-28T14:48:43.444Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/debugging</loc>
<lastmod>2026-07-28T14:48:43.414Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/io-interfaces</loc>
<lastmod>2026-07-28T14:48:43.387Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/clocking</loc>
<lastmod>2026-07-28T14:48:43.358Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-design</loc>
<lastmod>2026-07-28T14:48:43.330Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sync-design</loc>
<lastmod>2026-07-28T14:48:43.300Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-boards</loc>
<lastmod>2026-07-28T14:48:43.235Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/open-source-tools</loc>
<lastmod>2026-07-28T14:48:43.205Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-flow</loc>
<lastmod>2026-07-28T14:48:43.177Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-families</loc>
<lastmod>2026-07-28T14:48:43.147Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-architecture</loc>
<lastmod>2026-07-28T14:48:43.119Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-patterns</loc>
<lastmod>2026-07-28T14:48:43.071Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/simulation</loc>
<lastmod>2026-07-28T14:48:43.042Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/systemverilog</loc>
<lastmod>2026-07-28T14:48:43.014Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog</loc>
<lastmod>2026-07-28T14:48:42.986Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl</loc>
<lastmod>2026-07-28T14:48:42.956Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-intro</loc>
<lastmod>2026-07-28T14:48:42.925Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-basics</loc>
<lastmod>2026-07-28T14:48:58.531Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/state-machines</loc>
<lastmod>2026-07-28T14:48:58.476Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sequential-logic</loc>
<lastmod>2026-07-28T14:48:58.402Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/combinational-logic</loc>
<lastmod>2026-07-28T14:48:58.231Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/boolean-algebra</loc>
<lastmod>2026-07-28T14:48:58.172Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/number-systems</loc>
<lastmod>2026-07-28T14:48:58.339Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cdc/when-the-rtl-is-right-and-the-build-is-wrong</loc>
<lastmod>2026-07-28T14:48:57.951Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/timing-basics/a-nanosecond-is-a-distance</loc>
<lastmod>2026-07-28T14:48:56.599Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/cdc/clock-domain-crossing-every-way-to-get-it-wrong</loc>
<lastmod>2026-07-28T14:48:57.722Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
</urlset>
