<?xml version="1.0" encoding="UTF-8"?>
<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
<url>
<loc>https://rtl.academy/</loc>
<changefreq>weekly</changefreq>
<priority>1</priority>
</url>
<url>
<loc>https://rtl.academy/privacy</loc>
<changefreq>yearly</changefreq>
<priority>0.2</priority>
</url>
<url>
<loc>https://rtl.academy/career</loc>
<lastmod>2026-05-27T12:27:14.676Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-design-pipeline</loc>
<lastmod>2026-05-27T12:27:14.416Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/glossary</loc>
<lastmod>2026-05-27T12:27:03.549Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/tool-setup</loc>
<lastmod>2026-05-27T12:27:03.517Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sdc-reference</loc>
<lastmod>2026-05-27T12:27:03.486Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog-reference</loc>
<lastmod>2026-05-27T12:27:03.459Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl-reference</loc>
<lastmod>2026-05-27T12:27:03.431Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/motor-control</loc>
<lastmod>2026-05-27T12:27:03.381Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cryptography</loc>
<lastmod>2026-05-27T12:27:03.352Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ml-acceleration</loc>
<lastmod>2026-05-27T12:27:03.324Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/communications</loc>
<lastmod>2026-05-27T12:27:03.295Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/image-processing</loc>
<lastmod>2026-05-27T12:27:03.264Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/advanced-architecture</loc>
<lastmod>2026-05-27T12:27:03.215Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verification</loc>
<lastmod>2026-05-27T12:27:03.187Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hls</loc>
<lastmod>2026-05-27T12:27:03.158Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/embedded-processors</loc>
<lastmod>2026-05-27T12:27:03.131Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-interfaces</loc>
<lastmod>2026-05-27T12:27:03.103Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/high-speed-serial</loc>
<lastmod>2026-05-27T12:27:03.076Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dsp</loc>
<lastmod>2026-05-27T12:27:03.043Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/optimization</loc>
<lastmod>2026-05-27T12:27:02.996Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/ip-cores</loc>
<lastmod>2026-05-27T12:27:02.967Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/bus-architectures</loc>
<lastmod>2026-05-27T12:27:02.932Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/pipelining</loc>
<lastmod>2026-05-27T12:27:02.905Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/cdc</loc>
<lastmod>2026-05-27T12:27:14.622Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-closure</loc>
<lastmod>2026-05-27T12:27:02.824Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/projects</loc>
<lastmod>2026-05-27T12:27:02.780Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/debugging</loc>
<lastmod>2026-05-27T12:27:02.754Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/io-interfaces</loc>
<lastmod>2026-05-27T12:27:02.719Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/clocking</loc>
<lastmod>2026-05-27T12:27:02.645Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/memory-design</loc>
<lastmod>2026-05-27T12:27:02.600Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sync-design</loc>
<lastmod>2026-05-27T12:27:02.548Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-boards</loc>
<lastmod>2026-05-27T12:27:02.502Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/open-source-tools</loc>
<lastmod>2026-05-27T12:27:02.476Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/dev-flow</loc>
<lastmod>2026-05-27T12:27:02.448Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-families</loc>
<lastmod>2026-05-27T12:27:02.421Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/fpga-architecture</loc>
<lastmod>2026-05-27T12:27:02.392Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-patterns</loc>
<lastmod>2026-05-27T12:27:02.346Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/simulation</loc>
<lastmod>2026-05-27T12:27:02.318Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/systemverilog</loc>
<lastmod>2026-05-27T12:27:02.289Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/verilog</loc>
<lastmod>2026-05-27T12:27:02.253Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/vhdl</loc>
<lastmod>2026-05-27T12:27:02.219Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/hdl-intro</loc>
<lastmod>2026-05-27T12:27:02.187Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-basics</loc>
<lastmod>2026-05-27T12:27:14.558Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/state-machines</loc>
<lastmod>2026-05-27T12:27:02.022Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/sequential-logic</loc>
<lastmod>2026-05-27T12:27:01.990Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/combinational-logic</loc>
<lastmod>2026-05-27T12:27:01.958Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/boolean-algebra</loc>
<lastmod>2026-05-27T12:27:14.334Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/number-systems</loc>
<lastmod>2026-05-27T12:27:14.467Z</lastmod>
<changefreq>weekly</changefreq>
</url>
<url>
<loc>https://rtl.academy/timing-basics/a-nanosecond-is-a-distance-latency-budgets-from-first-principles</loc>
<lastmod>2026-05-27T12:27:13.848Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
<url>
<loc>https://rtl.academy/cdc/clock-domain-crossing-every-way-to-get-it-wrong</loc>
<lastmod>2026-05-27T12:27:14.068Z</lastmod>
<changefreq>monthly</changefreq>
<priority>0.8</priority>
</url>
</urlset>
